`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   15:08:32 12/09/2008
// Design Name:   VGARead
// Module Name:   C:/Documents and Settings/William Lee/My Documents/VGA/VGARead_tb.v
// Project Name:  VGA
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: VGARead
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module VGARead_tb;

	// Inputs
	reg clock;
	reg reset;
	reg [15:0] frontTileIndex;
	reg [15:0] backTileIndex;
	reg [15:0] frontPixelData;
	reg [15:0] backPixelData;
	reg [3:0] currentVerticalPixelCount;
	reg startToRead;

	// Outputs
	wire frontPixelDataEnable;
	wire backPixelDataEnable;
	wire writeBackTileEnable;
	wire writeFrontTileEnable;
	wire writePixelDataEnable;
	wire [4:0] tileIndex;
	wire [7:0] hPixelCount;
	wire [4:0] readTileIndex;
	wire [14:0] address;
	wire [15:0] pixelData;

	integer i = 0;
	// Instantiate the Unit Under Test (UUT)
	VGARead uut (
		.clock(clock), 
		.reset(reset), 
		.frontTileIndex(frontTileIndex), 
		.backTileIndex(backTileIndex), 
		.frontPixelData(frontPixelData), 
		.backPixelData(backPixelData), 
		.currentVerticalPixelCount(currentVerticalPixelCount), 
		.startToRead(startToRead), 
		.frontPixelDataEnable(frontPixelDataEnable), 
		.backPixelDataEnable(backPixelDataEnable), 
		.writeBackTileEnable(writeBackTileEnable), 
		.writeFrontTileEnable(writeFrontTileEnable), 
		.writePixelDataEnable(writePixelDataEnable), 
		.tileIndex(tileIndex), 
		.hPixelCount(hPixelCount), 
		.readTileIndex(readTileIndex), 
		.address(address), 
		.pixelData(pixelData)
	);

	initial begin
		// Initialize Inputs
		clock = 0;
		reset = 0;
		frontTileIndex = 0;
		backTileIndex = 0;
		frontPixelData = 0;
		backPixelData = 0;
		currentVerticalPixelCount = 0;
		startToRead = 0;

		// Wait 100 ns for global reset to finish
		#100;
		for(i = 0; i < 10; i = i + 1)
		begin
		#1
			clock = ~clock;
			if(i == 0)
				reset = 1;
			else if( i == 7)
					reset = 0;
			else if(i ==9)
					startToRead = 1;
				
		end
		end
        
		always
		begin
		#1 clock = ~clock;
		end
		// Add stimulus here

	
	
      
endmodule

